Compiling communicating processes into delay-insensitive VLSI circuits

Translating concurrent programs into delay-insensitive circuits

Erik Brunvand* Carnegie Mellon University Programs written in a subset of occam are automatically translated into delay-insensitive circuits using syntax-directed techniques. The resulting circuits are improved using semantics-preserving circuit-tocircuit transformations. Since each step of the translation process can be proven correct, the resulting circuit behavior is a faithful copy of the o...

Conservative Delay-Insensitive Circuits

Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits

Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions into potentially high speed, low cost and very robust circuits, called delay-insensitive combinational tree iterative circuits. In particular, our methodology can be applied to synthesize binary addition and comparison...

Controllable Delay-Insensitive Processes

Josephs and Udding’s DI-Algebra offers a convenient way of specifying and verifying designs that must rely upon delay-insensitive signalling between modules (asynchronous logic blocks). It is based on Hoare’s theory of CSP, including the notion of refinement between processes, and is similarly underpinned by a denotational semantics. Verhoeff developed an alternative theory of delay-insensitive...

Compiling Esterel into Better Circuits

Producing efficient circuits from a high-level language such as Esterel remains a problem. Sparse state coding requires many more latches used than minimum and waste of reachable state space, while tight state encoding produces slow circuits due to the cost of encoding and decoding. This paper presents an algorithm to generate small and fast circuitry for Esterel. There are three main parts of ...